module DECODER_5bit(in, out);
input [4:0] in;
output [31:0] out;
wire [15:0] DecodedData;
wire Nin;


assign Nin = ~in[4];
DECODER_4bit Dec4(in[3:0], DecodedData[15:0]);
//or(out[15:0], in[4], DecodedData[15:0]);

and(out[31], in[4], DecodedData[15]);
and(out[30], in[4], DecodedData[14]);
and(out[29], in[4], DecodedData[13]);
and(out[28], in[4], DecodedData[12]);
and(out[27], in[4], DecodedData[11]);
and(out[26], in[4], DecodedData[10]);
and(out[25], in[4], DecodedData[9]);
and(out[24], in[4], DecodedData[8]);
and(out[23], in[4], DecodedData[7]);
and(out[22], in[4], DecodedData[6]);
and(out[21], in[4], DecodedData[5]);
and(out[20], in[4], DecodedData[4]);
and(out[19], in[4], DecodedData[3]);
and(out[18], in[4], DecodedData[2]);
and(out[17], in[4], DecodedData[1]);
and(out[16], in[4], DecodedData[0]);

and(out[15], Nin, DecodedData[15]);
and(out[14], Nin, DecodedData[14]);
and(out[13], Nin, DecodedData[13]);
and(out[12], Nin, DecodedData[12]);
and(out[11], Nin, DecodedData[11]);
and(out[10], Nin, DecodedData[10]);
and(out[9], Nin, DecodedData[9]);
and(out[8], Nin, DecodedData[8]);
and(out[7], Nin, DecodedData[7]);
and(out[6], Nin, DecodedData[6]);
and(out[5], Nin, DecodedData[5]);
and(out[4], Nin, DecodedData[4]);
and(out[3], Nin, DecodedData[3]);
and(out[2], Nin, DecodedData[2]);
and(out[1], Nin, DecodedData[1]);
and(out[0], Nin, DecodedData[0]);

endmodule


module DECODER_4bit(in, out);
input [3:0] in;
output [15:0] out;
wire [7:0] DecodedData;
wire Nin;

assign Nin = ~in[3];
DECODER_3bit Dec3(in[2:0], DecodedData[7:0]);

and(out[15], in[3], DecodedData[7]);
and(out[14], in[3], DecodedData[6]);
and(out[13], in[3], DecodedData[5]);
and(out[12], in[3], DecodedData[4]);
and(out[11], in[3], DecodedData[3]);
and(out[10], in[3], DecodedData[2]);
and(out[9], in[3], DecodedData[1]);
and(out[8], in[3], DecodedData[0]);

and(out[7], Nin, DecodedData[7]);
and(out[6], Nin, DecodedData[6]);
and(out[5], Nin, DecodedData[5]);
and(out[4], Nin, DecodedData[4]);
and(out[3], Nin, DecodedData[3]);
and(out[2], Nin, DecodedData[2]);
and(out[1], Nin, DecodedData[1]);
and(out[0], Nin, DecodedData[0]);


endmodule


module DECODER_3bit(in, out);
input [2:0] in;
output [7:0] out;
wire [3:0] DecodedData;
wire Nin;
assign Nin = ~in[2];
DECODER_2bit Dec2(in[1:0], DecodedData[3:0]);


and(out[7], in[2], DecodedData[3]);
and(out[6], in[2], DecodedData[2]);
and(out[5], in[2], DecodedData[1]);
and(out[4], in[2], DecodedData[0]);


and(out[3], Nin, DecodedData[3]);
and(out[2], Nin, DecodedData[2]);
and(out[1], Nin, DecodedData[1]);
and(out[0], Nin, DecodedData[0]);

endmodule

module DECODER_2bit(in, out);
input [1:0] in;
output [3:0] out;
wire [1:0] Nin;

assign Nin = ~in;

and a1(out[0], Nin[1], Nin[0]);
and a2(out[1], Nin[1], in[0]);
and a3(out[2], in[1], Nin[0]);
and a4(out[3], in[1], in[0]);

endmodule

